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Description of my self build +3s.
The “s” suffix comes from my nick name, Secărică ...
- Overall characteristics
- Some functional details
- ...
(i) Overall characteristics
I started this project sometime back in 1989.
What was in my mind at that time ?
Simple things ...
- to have a computer that is compatible with the original +3 Spectrum
- to be able to turn the computer in 48K, +128 or +2 mode, if so desired
- to be able to run CP/M
... and advanced things
- to be able to run the computer also at a greater clock speed
- to be able to run the CP/M in 80 column display at a time (with no screen switching)
- to be able to spy a game code during its play and have the capability to change anything there
- to be able to hack any kind of software loading protection scheme, disk or tape
- to have TV standard synchronization pulses timing
- to have genlock capabilities with an external video source
- to be able to take video snapshots (1 bit per pixel)
And the result ?
Today I have an 8 bit computer that ...
- is 99% downward compatible with the original +3 Spectrum
- uses 100% standard logic integrated circuits (mixed LS, ALS, HCT and HC series; no ULA/gate_array/whatever stuff)
- is equipped with a 20 MHz Z80 CMOS processor (Z84C0020PEC)
- the CPU actually runs at 3.5MHz, 7MHz, or 14MHz; the three modes are dynamically switchable (hardware and/or software switching; two bits of a configuration port)
- the 3.5MHz and 7MHz clock are synchronous with the video circuits, since they are originate from the same oscillator; the internal (default) 14MHz also, but this third CPU clock can be relatively easy changed to other external totally independent clock, from down to any value (but still limited by the RAM refresh cycles), to up to approximately 15MHz
- I first used a 10 MHz Z80 CMOS processor (Z84C0010PEC), which worked well overclocked at 14MHz, but I finally got the 20MHz version
- is equipped with the +3 ROMs
- a slightly modified version; on +3, the CPU communicates with the FDD controller in polling mode (as opposed to interrupt driven mode), so the software timing is somewhat critical; the modification takes into account the actual CPU speed and enters different software timing loops for 3.5MHz, 7MHz and 14MHz
- is equipped with 1024K RAM, divided in 64 pages x 16K each (logical pages 0-59)
- RAM pages 0-7 are addressed in the same manner like the original +3
- RAM pages 8-59 can be switched at address C000h-FFFFh (+128 Basic) or 4000h-7FFFh (CP/M) with custom software
- a special mode allows RAM pages 12-15 to work as shadow RAM for address 0000h-3FFFh
- is equipped with 64K video RAM, divided in 4 pages x 16K each, that normally works as shadow RAM for RAM pages 3-7
- in normal operation, video RAM is written by the CPU and read by video display circuits
- in normal operation, the CPU writes the same data both in RAM pages 3-7 and video RAM
- a special mode allows the CPU to write only to RAM pages 3-7, or only to video RAM
- a special mode allows the CPU to read from video RAM insted of RAM pages 3-7
- a special mode allows portion of video RAM to be written with serial data from an external video source (1 bit per pixel sampling); as the CPU can read data from video RAM separately from RAM pages 3-7, this allows aquisition and saving of the external video data from video RAM (i.e. the screen) for any further use (the video capture is similar to that obtained with Romantic Robot’s Videoface interface)
- is able to switch the video RAM in high resolution mode (page 5 and 7 together, each occupying half of the original Spectrum area - page 5 in the left side, page 7 in the right side)
- although this mode gives the same 512x192 screen resolution as the Timex 20x8 series does, the approach here is different: each half screen is a complete standard Spectrum screen, including attributes (no alternate columns concept is used)
- is able to boot in any official Spectrum ROM configuration, with the help of shadow RAM for address 0000h-3FFFh (the desired ROM content can be loaded from floppy in memory pages 12-15, then make the shadow RAM visible and boot in that configuration)
- uses dual address and data buffers for write operation to video RAM; this way, in normal operation mode, RAM code execution is at full speed in all pages for 3.5MHz and 7MHz CPU clock and with low percent WAIT states code execution in pages 3-7 for 14MHz CPU clock
- is able to switch off the H and/or V border, allowing the TV display area to show various video RAM addresses (software switching; two bits of a configuration port)
- is equipped with GI’s AY-3-8910 sound processor
- is equipped with I8272 equivalent FDD controller (Z0765A08PSC)
- is equipped with two 3.5” 1.44M HD floppy disk drives
- the FDD controller is able run at 4MHz or 8MHz, being able to use 720K DSDD and/or 1.44M DSHD floppy disks (independent DIP switches selection for each physical drive; any given disk type is not dynamically switchable (may need machine reboot)); 1.44M DSHD floppies are only usable at 7MHz or 14MHz CPU clock
- the original 3” can substitute any of the 3.5” drives, if so desired (physical hardware substitution, i.e. unconnect/reconnect the data and power cable; this may change in the future, to make the substitution easier)
- has one RGB video output
- has one PAL and one S-Video output, based on Analog Device’s AD722 RGB encoder; the subcarrier is locked to the horizontal sync pulses by using the 4Fsc horizontal genlock circuit from Intersil, EL4584 (former Elantec) and a 17.734475 MHz VCO recovered from a broken broadcast Sony video camera (but the subcarrier lock is not mandatory for the AD722 to work properly, it was just my hobby :)
- I first used the Philips TEA2000 video encoder, but in 2004 I changed it with Analog Device AD722, because AD722 also offers S-Video output; the video board now looks like this (or this, this and this) and for the moment it is the only part built on special designed circuit board
- is able to genlock the video circuits to an external video signal; the free run mode <-> genlock mode is dynamically switchable (hardware and/or software switching; two bits of a configuration port) (project not finished)
- is able to change the video V resolution from 313 lines @50Hz (default) to 312 lines @50Hz or 625 lines @25Hz interlaced (two identical 312.5 lines field), in order to accomodate to various video signal input types; the three modes are dynamically switchable (hardware and/or software switching; two bits of a configuration port)
- has the hardware interrupt signal rate of 50Hz (always), at fixed position, no matter the CPU speed
- has the border timing similar to the Spectrum 48K version; this way Aqua Plane (for example) has the water/sky horizon at the right place, when playing at 3.5MHz
- uses synchronous reset circuits, to keep alive RAM refresh during reset cycle; applies to CPU, FDD, PSG and all output ports; video RAM circuits are never reset
- has a reverse reset action of the Centronics parallel port nSTROBE signal (bit4 / OUT #1FFD port), in that nSTROBE is forced to 1 logic state at reset time; this assures that the printer will not collect garbage at reste time
- is able to run Locomotive Software CP/M Plus for +3 (but not other CP/M implementation(s), as originally intended)
- has complete address decoding for all ports
- has read status capabilities for all ports, except for the border, tape & beep port (OUT #FE) and the Centronics parallel printer port (OUT #0FFD)
- has an extended keyboard column connected to bit5 / IN #FE port, giving 8 new keys; the new keys are named F1 to F8 and are used by custom software only
- has a built-in Kempston joystick port (software enable/disable switch; one bit of a configuration port; default is disable)
- has a true IN #FF port for video timing reading, in order to make games compatible with the old 48k, 128K and +2 Spectrum; however, only bit7 is taken into consideration
- is equipped with Motorola 6818 equivalent real time clock (HD146818); the purpose is to have real time clock under CP/M (project not finished)
... and it has only one noticeable limitation
- has no standard ZX Spectrum type expansion port connector; external bus is available, but a physical adapter is required for original Spectrum peripherals (not available at the moment; in the last 10 years of Spectrum experience I have not found any reason for building it :)
There are also a few things I am planning to do in the future. I have no idea if and which of those things will ever be done.
For example, I want to change the CP/M actual 24x80 flip screen 5x8 pixel character display to a true 24x80 8x8 pixel character. The hardware permits this, but involves a lot of work in disassembling the original CP/M routines and to discover all cross interactions when changing something there.
I also have to finish the real time clock circuit. At present, when booting CP/M, I am entering the date & time manually each time and I find this very annoying. I like to automate this process. The only thing I don’t know, is whether or not the circuit I am using has Y2K problems.
(ii) Some functional details
Reset
There are 3 reset modes:
- n/POWER_ON_RESET; asynchronous; will reset CPU, FDD, PSG and all output ports, will force 3.5 MHz processor clock and local free run mode oscillator for video circuits; duration is undetermined;
RAM refresh cycles are not guaranteed during this reset type;
normally, this reset only occurs when powering the system, but it can be forced at anytime by pressing a (hidden) button
- n/SYSTEM_RESET; synchronous; will reset CPU, FDD, PSG and all output ports; duration is 2 µs;
RAM refresh cycles are preserved during this reset type, therefore, as an example, a ROM content loaded in RAM for later use as the boot choice will not be affected
- n/+3_RESET; synchronous; will reset CPU, FDD, PSG and only original +3 Spectrum output ports; duration is 2 µs;
RAM refresh cycles are preserved during this reset type, therefore, as an example, a ROM content loaded in RAM for later or immediate use as the boot choice will not be affected
I/O Ports
Summary
- #1F (Kempston joystick)
- #FE (border, keyboard, tape)
- #FF (synchronization with active video area for some games)
- #0FFD (parallel printer port)
- #1FFD (memory paging, parallel printer port strobe, FDD motor)
- #2FFD (FDD interface)
- #3FFD (FDD interface)
- #7FFD (memory paging, 48K lock)
- #BFFD (PSG interface)
- #FFFD (PSG interface)
- #7F7E (RAM shadow for ROM handling, misc hardware settings)
- #BF7E (video RAM access handling)
- #DF7E (extra memory paging)
- #EF7E (misc hardware settings)
All ports are fully decoded.
Detailed
Original +3 ports, or ports that are traditionally used by Spectrum software
With the exception of port #1F and #FF, all ports behaves the same as for the original +3, except that input ports #1FFD and #7FFD have read capabilities (e.g. bits 0-5 / port IN #7FFD will read the actual status of port OUT #7FFD) and the unused bits of input ports #FE, #1FFD and #7FFD are used to read various machine parameter status.
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port #1F (31)
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OUT
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IN
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bit 0
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not used
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Kempston joystick * - right
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bit 1
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not used
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Kempston joystick * - left
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bit 2
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not used
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Kempston joystick * - down
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bit 3
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not used
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Kempston joystick * - right
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bit 4
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not used
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Kempston joystick * - fire
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bit 5
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not used
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not used
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bit 6
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not used
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not used
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bit 7
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not used
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not used
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* Only when Kempston joystick is enabled, via custom bit 7 / OUT #BF7E
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port #FE (254)
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OUT
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IN
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bit value = 0
(default at any RESET)
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bit value = 1
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bit 0
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B border color OFF
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B border color ON
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keyboard column CSHIFT, A, Q, 1, 0, P, ENT, SPACE
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bit 1
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R border color OFF
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R border color ON
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keyboard column Z, S, W, 2, 9, O, L, SSHIFT
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bit 2
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G border color OFF
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G border color ON
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keyboard column X, D, E, 3, 8, O, K, M
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bit 3
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tape data out
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keyboard column C, F, R, 4, 7, U, J, N
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bit 4
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48K beep out
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keyboard column V, G, T, 5, 6, Y, H, B
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bit 5
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tape motor OFF
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tape motor ON
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keyboard column F1, F2, ..., F8
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bit 6
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not used
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not used
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tape data in
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bit 7
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not used
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not used
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if 1 => video circuit oscillator is in external mode
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 color = additional I/O port usage, when comparing to original +3
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port #1FFD (8189)
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OUT
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IN
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bit value = 0
(default at any RESET,
except for bit 4)
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bit value = 1
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bit 0
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main RAM is in +3 Basic mode
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main RAM is in CP/M mode
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actual bit status
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bit 1
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see the +3 documentation for this one
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actual bit status
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bit 2
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see the +3 documentation for this one
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actual bit status
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bit 3
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FDD motor OFF
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FDD motor ON
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actual bit status
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bit 4
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parallel printer port n/STROBE out
this bit is set at any RESET
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actual bit status
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bit 5
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not used
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not used
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if 1 => 3.5 MHz CPU clock
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bit 6
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not used
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not used
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if 1 => 7 MHz CPU clock
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bit 7
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not used
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not used
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if 1 => 14 MHz CPU clock
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color = additional I/O port usage, when comparing to original +3
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port #7FFD (32765)
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OUT
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IN
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bit value = 0
(default at any RESET)
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bit value = 1
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bit 0
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see the +3 documentation for these ones
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actual bit status
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bit 1
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actual bit status
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bit 2
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actual bit status
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bit 3
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in normal screen resolution
display is video RAM pge 5
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in normal screen resolution
display is video RAM page 7
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actual bit status
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bit 4
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see the +3 documentation for this one
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actual bit status
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bit 5
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ports #1FFD and #7FFD are unlocked
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ports #1FFD and #7FFD are locked
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actual bit status
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bit 6
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not used
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not used
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n/H_BLANK
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bit 7
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not used
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not used
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n/V_BLANK
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color = additional I/O port usage, when comparing to original +3
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port #FF (255)
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OUT
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IN
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bit 0
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not used
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not used
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bit 1
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not used
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not used
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bit 2
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not used
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not used
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bit 3
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not used
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not used
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bit 4
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not used
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not used
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bit 5
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not used
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not used
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bit 6
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not used
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not used
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bit 7
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not used
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n/ACTIVE_WINDOW (H border AND-ed with V border)
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All the other +3 ports (#0FFD for parallel printer, #2FFD & #3FFD for FDD interface and #BFFD & FFFD for PSG interface) are implemented the same as on original +3.
Custom I/O ports, not found on original Spectrum hardware
All of these new ports have read capabilities (i.e. an IN #xxxx instruction will read the actual status of that #xxxx port).
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port #7F7E (32638)
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OUT
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IN
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bit value = 0
(default at system reset)
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bit value = 1
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bit 0
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ROM page 0 at address
0000-3FFF *
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RAM page 12 at address
0000-3FFF *
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actual bit status
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bit 1
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ROM page 1 at address
0000-3FFF *
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RAM page 13 at address
0000-3FFF *
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actual bit status
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bit 2
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ROM page 2 at address
0000-3FFF *
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RAM page 14 at address
0000-3FFF *
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actual bit status
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bit 3
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ROM page 3 at address
0000-3FFF *
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RAM page 15 at address
0000-3FFF *
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actual bit status
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bit 4
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write enable RAM pages
12-15 when in ROM mode
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write disable RAM pages
12-15 when in ROM mode
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actual bit status
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bit 5
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48K lock enable
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48K lock disable
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actual bit status
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bit 6
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normal H border
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H border suppressed
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actual bit status
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bit 7
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normal V border
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V border suppressed
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actual bit status
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* Actual ROM (or RAM in ROM mode) page at address 0000-3FFF depends on original +3 ports #1FFD and #7FFD status
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port #BF7E (49022)
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OUT
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IN
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bit value = 0
(default at system reset)
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bit value = 1
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bit 0
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write enable video RAM
for first 8K of page 5
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write disable video RAM
for first 8K of page 5
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actual bit status
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bit 1
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write enable video RAM
for first 8K of page 7
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write disable video RAM
for first 8K of page 7
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actual bit status
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bit 2
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write enable video RAM
for second 8K of pages 5 & 7
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write disable video RAM
for second 8K of pages 5& 7
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actual bit status
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bit 3
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write enable video RAM
for pages 4 & 6
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write disable video RAM
for pages 4 & 6
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actual bit status
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bit 4
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write enable main RAM
for pages 4-7
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write disablemain RAM
for pages 4-7
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actual bit status
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bit 5
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CPU reads pages 4-7
from main RAM
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CPU reads pages 4-7
from video RAM
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actual bit status
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bit 6
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normal H resolution
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double H resolution
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actual bit status
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bit 7
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video RAM is written by CPU
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video RAM is written by external serial data
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actual bit status
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port #DF7E (57214)
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OUT
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IN
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bit value = 0
(default at system reset)
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bit value = 1
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bit 0
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not used at present
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not used at present
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actual bit status
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bit 1
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not used at present
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not used at present
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actual bit status
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bit 2
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not used at present
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not used at present
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actual bit status
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bit 3
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extends main RAM to 256K at address C000-FFFF (+3 mode) or 4000-7FFF (CP/M Plus mode)
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actual bit status
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bit 4
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extends main RAM to 512K at address C000-FFFF (+3 mode) or 4000-7FFF (CP/M Plus mode)
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actual bit status
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bit 5
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extends main RAM to 1024K at address C000-FFFF (+3 mode) or 4000-7FFF (CP/M Plus mode)
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actual bit status
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bit 6
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not used at present
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not used at present
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actual bit status
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bit 7
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not used at present
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not used at present
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actual bit status
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port #EF7E (61310)
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OUT
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IN
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bit value = 0
(default at system reset)
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bit value = 1
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bit 0
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00 - no change, allows hardware switching
01 - force 3.5 MHz CPU clock
10 - force 7 MHz CPU clock
11 - force 14 MHz CPU clock
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actual bit status
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bit 1
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actual bit status
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bit 2
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00 - no change, allows hardware switching
01 - force local free run oscillator for video circuits
10 - force external oscillator for video circuits
11 - does nothing (considered as invalid)
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actual bit status
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bit 3
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actual bit status
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bit 4
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00 - display is 50 Hz / 313 lines
01 - display is 50 Hz / 312 lines
10 - display is 25 Hz / 625 lines interlaced (TV standard)
11 - display is 25 Hz / 625 lines interlaced (TV standard)
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actual bit status
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bit 5
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actual bit status
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bit 6
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tape IN port is free
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tape IN port is AND-ed with tape OUT
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actual bit status
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bit 7
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Kempston joystick disable
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Kempston joystick enable
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actual bit status
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Screen coverage of Video RAM addresses
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