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Description of my self build +3s. The “s” suffix comes from my nick name, Secărică.

This appears to be a never ending project, with some new ideas and solutions appearing after each previously applied ideas and solutions, with less and less time these days to advance efficiently. However, I still hope to advance anytime soon.

  1. Overall technical specifications
  2. Some functional details
  3. Drawings

(i) Overall technical specifications

I started this project sometime back in 1989.
What was in my mind at that time ?

Simple things ...

  • to have a computer that is compatible with the original +3 Spectrum
  • to be able to turn the computer in 48K, 128K or +2 mode, if so desired
  • to be able to run CP/M

... and advanced things

  • to be able to run the computer also at a greater clock speed
  • to be able to run the CP/M in 80 column display at once (with no screen switching)
  • to be able to spy a game code during its play and have the capability to change anything there
  • to be able to hack any kind of software loading protection scheme, disk or tape, without affecting the code of the software itself
  • to have broadcast quality sync timing on TV output
  • to have genlock capabilities from an external video source
  • to be able to take video snapshots (1 bit per pixel) from external video source, quite similar to that obtained with the Data-Skip / Romantic Robot Videoface Digitizer interface)

And the result ?

+3s main board – components side
Components side of my +3s main board as it was in 2002; FDD controller and 128K sound are on separate boards
+3s main board – wiring side
Wiring side of my +3s main board as it was in 2002 (wires are solid copper, not wrap wire)

Today I have an 8 bit computer that ...

  • is 99% backward compatible with the original +3 Spectrum
  • uses 100% standard logic integrated circuits (mixed LS, ALS, HCT and HC series; no ULA/gate_array/whatever stuff)
  • is equipped with a 20 MHz Z80 CMOS processor (Z84C0020PEC )
    • the CPU actually runs at 3.5MHz, 7MHz, or 14MHz; the three modes are dynamically switchable (hardware and/or software switching; two bits of a configuration port)
    • the 3.5MHz and 7MHz clock are synchronous with the video circuits, since they originate from the same quartz oscillator; the internal (default) 14MHz also, but this third CPU clock can be relatively easy changed to an independent external free running clock, from down to any frequency value (but still limited by the RAM refresh cycles), to up to approximately 16MHz
    • I first used a 10 MHz Z80 CMOS processor (Z84C0010PEC), which worked well overclocked at 14MHz, but I finally got the 20MHz version
  • is equipped with the +3 ROMs
    • a slightly modified version; on +3, the CPU communicates with the FDD controller in polling mode (as opposed to interrupt driven mode), so the software timing is somewhat critical; the modification takes into account the actual CPU speed and introduces different software timing loops for 3.5MHz, 7MHz and 14MHz
  • is equipped with 256K RAM, divided in 16 logical pages × 16K each
    (physical memory type will change from 2*256K×4bit RAM to one 32 pin SIMM module during the next hardware revision, allowing memory upgrade up to 4096K RAM, resulting in up to 256 logical pages)
    • RAM pages 0-7 are addressed in exactly the same manner as the original +3
    • RAM pages 8-11 can be switched at address C000h-FFFFh (+128 Basic) or 4000h-7FFFh (CP/M) with custom software
    • a special mode allows RAM pages 12-15 to work as shadow RAM for address 0000h-3FFFh
  • is able to boot in any official or modified ZX Spectrum ROM configuration, when switching the shadow RAM at address 0000h-3FFFh
    (the desired ROM content can be loaded from disk drive in memory pages 12‑15, then make the shadow RAM visible and boot in that configuration)
  • is equipped with 64K video RAM, divided in 4 logical pages × 16K each, that normally works as shadow RAM for RAM pages 3-7
    • in normal operation, video RAM is written by the CPU and read by video display circuits
    • in normal operation, the CPU writes the same data both in RAM pages 3-7 and video RAM
    • a special mode allows the CPU to write only to RAM pages 3-7, or only to video RAM
    • a special mode allows the CPU to read from video RAM instead of RAM pages 3-7
    • a special mode allows portion of video RAM to be written with serial data from an external video source (1 bit per pixel sampling); as the CPU can read data from video RAM separately from RAM pages 3-7, this allows acquisition and saving of the external video data from video RAM (i.e. the screen) for any further use
  • is able to switch the video RAM in double resolution mode (page 5 and 7 together, each occupying half of the original Spectrum area - page 5 in the left side, page 7 in the right side)
    • although this mode gives the same 512x192 screen resolution as the Timex 20x8 series does, the approach here is different: each half screen is a complete standard Spectrum screen, including attributes (no alternate columns concept is used)
  • uses dual address and data buffers for write operation to video RAM; because of this, in normal operation mode, RAM code execution is at full speed in all pages for 3.5MHz and 7MHz CPU clock and with low percent WAIT states code execution in pages 3-7 for 14MHz CPU clock
  • is able to switch off the H and/or V border, allowing the TV display area to show various video RAM addresses (software switching; two bits of a configuration port)
  • is equipped with GI’s AY-3-8910 sound processor
  • is equipped with I8272 equivalent FDD controller (Z0765A08PSC)
  • is equipped with two 3.5” 1.44M HD floppy disk drives
    • the FDD controller is able run at 4MHz or 8MHz, being able to use 720K DSDD and/or 1.44M DSHD floppy disks (independent DIP switches selection for each physical drive; any given disk type is not dynamically switchable (may need machine reboot))
      (1.44M DSHD floppies are only usable at 7MHz or 14MHz CPU clock)
    • the original 3” can substitute any of the 3.5” drives, if so desired (physical hardware substitution, i.e. unconnect/reconnect the data and power cable; this may change in the future, to make the substitution easier)
  • has one RGB video output
  • has one PAL and one S-Video output, based on Analog Device’s AD722 RGB encoder; the subcarrier is locked to the horizontal sync pulses by using the 4Fsc horizontal genlock circuit from Intersil, EL4584 (former Elantec) and a 17.734475 MHz VCO recovered from a broken broadcast Sony video camera (but the subcarrier lock is not mandatory for the AD722 to work properly, this was just my hobby :)
    • at first I used the Philips TEA2000 video encoder like in original +128/+2/+3, but in 2004 I changed it with Analog Device AD722, because AD722 also offers S‑Video output; the video board now looks like this and for the moment it is the only part built on printed circuit board; I shaped a PCI-like board outline in case someday I will use a disaffected PC case for housing of my +3s, except that today I think that was a bad idea (I should build a specific case for it, something that actually existed at one point)
  • is able to genlock the video circuits to an external video signal; the free run mode <-> genlock mode is dynamically switchable (hardware and/or software switching; two bits of a configuration port) (project not finished)
  • is able to change the video V resolution from 313 lines @50Hz (default) to 312 lines @50Hz or 625 lines @25Hz interlaced (two identical 312.5 lines field), in order to accommodate to various video signal input types; the three modes are dynamically switchable (hardware and/or software switching; two bits of a configuration port)
  • has the hardware interrupt signal rate of 50Hz (always), at fixed position, no matter the CPU speed
  • has the border timing similar to the Spectrum 48K version; this way Aqua Plane (for example) has the water/sky horizon at the right place, when playing at 3.5MHz
  • uses synchronous reset circuits, to keep alive RAM refresh during reset cycle; applies to CPU, FDD, PSG and all output ports; video RAM circuits are never reset
  • has a reverse reset action of the Centronics parallel port nSTROBE signal (bit4 / OUT #1FFD port), in that nSTROBE is forced to 1 logic state at reset time; this ensures that the printer will not collect garbage at reset time
  • is able to run Locomotive Software CP/M Plus for +3 (but not other CP/M implementation(s), as originally intended)
  • has complete address decoding for all ports
  • has read status capabilities for all ports, except for the border, tape & beep port (OUT #FE) and the Centronics parallel printer port (OUT #0FFD)
  • has an extended keyboard column connected to bit5 / IN #FE port, giving 8 new keys; the new keys are named F1 to F8 and can be used by custom software
  • has a built-in Kempston joystick port (software enable/disable switch; one bit of a configuration port; default is disable)
  • has a true IN #FF port for video timing reading, in order to make games compatible with the old 48k, 128K and +2 Spectrum; however, only bit7 is taken into consideration

... and it has only one noticeable limitation

  • has no standard ZX Spectrum type expansion port connector; external bus is available, but a physical adapter is required for original Spectrum peripherals (not available at the moment; in the last ~20 years of ZX Spectrum experience I have not found any reason for building it :)

There are also a few things I am still planning to do in the future. I have no idea if and which of those things will ever be done.

For example, I want to change the CP/M actual 24x80 flip screen 5x8 pixel character display to a true 24x80 8x8 pixel character. The hardware permits this, but involves a lot of work in disassembling the original CP/M routines and discover all cross interactions when changing something there.

I also want to build a real time clock circuit. At present, when booting CP/M, I am entering the date & time manually each time and I find this very annoying. I would like to automate this process.

Other thing is that I am not interested in attaching a hard drive, but I am interested in attaching a SD memory card, even as a floppy replacement, no matter how slow the access speed will result. But one of the problem is that the internet today has become too commercial, superficial and less informative from an engineering point of view: I can find tons of places where I can buy an SD memory card, I can read several stories about how to use an SD memory card, but it is more and more difficult to find a place that describes its truly technical functionality. I mean truly: timings, bus voltage tolerance, consumption in various scenarios, bus protocol instructions, etc.


(ii) Some functional details

Reset

There are 3 reset modes:

  • n/POWER_ON_RESET; asynchronous; will reset CPU, FDD, PSG and all output ports, will force 3.5 MHz processor clock and local free run mode oscillator for video circuits; duration is undetermined;
    RAM refresh cycles are not guaranteed during this reset type;
    normally, this reset only occurs when powering the system, but it can be forced at anytime by pressing a (hidden) hardware button
  • n/SYSTEM_RESET; synchronous; will reset CPU, FDD, PSG and all output ports; duration is 2 µs;
    RAM refresh cycles are preserved during this reset type, therefore, as an example, a ROM content loaded in RAM for later use as the boot choice will not be affected
  • n/+3_RESET; synchronous; will reset CPU, FDD, PSG and only original +3 Spectrum output ports; duration is 2 µs;
    RAM refresh cycles are preserved during this reset type, therefore, as an example, a ROM content loaded in RAM for later or immediate use as the boot choice will not be affected

I/O Ports

Summary
  • #1F (traditional third party; Kempston joystick)
  • #FE (original on all models; keyboard, border, beep, tape)
  • #FF (original behaviour on 48K/128K/+2 models; used sometimes to sync software with active video area)
  • #0FFD (original on +2A/+3 models; parallel printer port)
  • #1FFD (original on +2A/+3 models; memory paging, parallel printer port strobe, FDD motor)
  • #2FFD (original on +2A/+3 models; FDD interface (on +2A it could be considered as “reserved”))
  • #3FFD (original on +2A/+3 models; FDD interface (on +2A it could be considered as “reserved”))
  • #7FFD (original on 128K/+2/+2A/+3 models; memory paging, 48K lock)
  • #BFFD (original on 128K/+2/+2A/+3 models; PSG interface)
  • #FFFD (original on 128K/+2/+2A/+3 models; PSG interface)
  • #7F7E (custom; RAM shadow for ROM handling, misc hardware settings)
  • #BF7E (custom; video RAM access handling)
  • #DF7E (custom; extra memory paging)
  • #EF7E (custom; misc hardware settings)

All ports are fully decoded.

Original +48K Spectrum used only A0 for decoding its single port for keyboard, border, beep and tape, so any other hardware who wanted to be compatible with the physical 48K model was forced to use only odd I/O port numbers (a typical example is the Kempston joystick port); later, oficial models also used only odd port numbers for their various additional I/O . Since I was convinced that no software will ever try to access any even port number other than the original #xxFE, combined with the fact that I have no way to know if or what other odd port number could already be used by some commercial (or not) interface, the full port decoding gave me complete freedom to use any custom even I/O port from the 32512 ports available in the even range (i.e. less the original #xxFE). Having said that, I had no particular reason for choosing one value or another for my custom I/O ports.

Detailed
Original +3 ports, or ports that are traditionally used by Spectrum software

With the exception of port #1F and #FF, all ports behaves exactly the same as for the original +3, with the added bonus that input ports #1FFD and #7FFD also have read capabilities (i.e. a program can get the actual status of memory paging by issuing an IN #7FFD instruction, for example).

IN #7FFD will read the actual status of port OUT #7FFD; likewise, IN #1FFD will read the actual status of port OUT #1FFD. Additionally, originally unused bits of ports #FE, #1FFD and #7FFD are used in input to read various machine parameter status, with no interference with existing software.

port #1F (31)
  OUT IN
bit 0 not used * Kempston joystick - right
bit 1 not used * Kempston joystick - left
bit 2 not used * Kempston joystick - down
bit 3 not used * Kempston joystick - up
bit 4 not used * Kempston joystick - fire
bit 5 not used not used
bit 6 not used not used
bit 7 not used not used
* Only when Kempston joystick is enabled, via custom bit 7 / OUT #BF7E
port #FE (254)
  OUT IN
  bit value = 0
(default at any RESET)
bit value = 1  
bit 0 B border colour OFF B border colour ON keyboard column CSHIFT, A, Q, 1, 0, P, ENT, SPACE
bit 1 R border colour OFF R border colour ON keyboard column Z, S, W, 2, 9, O, L, SSHIFT
bit 2 G border colour OFF G border colour ON keyboard column X, D, E, 3, 8, O, K, M
bit 3 tape data OUT keyboard column C, F, R, 4, 7, U, J, N
bit 4 48K beep OUT keyboard column V, G, T, 5, 6, Y, H, B
bit 5 * tape motor OFF * tape motor ON * keyboard column F1, F2, F3, F4, F5, F6, F7, F8
bit 6 not used not used tape data IN
bit 7 not used not used * if 1 => video circuit oscillator is in external mode
* Additional I/O port usage, when comparing to original +3
port #1FFD (8189)
  OUT IN
  bit value = 0
(default at any RESET, except for bit 4)
bit value = 1  
bit 0 main RAM is in +3 Basic mode main RAM is in CP/M mode actual bit status
bit 1 see the +3 documentation for this one actual bit status
bit 2 see the +3 documentation for this one actual bit status
bit 3 FDD motor OFF FDD motor ON actual bit status
bit 4 parallel printer port n/STROBE out
this bit is set at any RESET
actual bit status
bit 5 not used not used if 1 => 3.5 MHz CPU clock
bit 6 not used not used if 1 => 7 MHz CPU clock
bit 7 not used not used if 1 => 14 MHz CPU clock
* Additional I/O port usage, when comparing to original +3
port #7FFD (32765)
  OUT IN
  bit value = 0
(default at any RESET)
bit value = 1  
bit 0 see the +3 documentation for this one actual bit status
bit 1 actual bit status
bit 2 actual bit status
bit 3 in normal screen resolution
display is video RAM page 5
in normal screen resolution
display is video RAM page 7
actual bit status
bit 4 see the +3 documentation for this one actual bit status
bit 5 ports #1FFD and #7FFD are unlocked ports #1FFD and #7FFD are locked actual bit status
bit 6 not used not used n/H_BLANK
bit 7 not used not used n/V_BLANK
* Additional I/O port usage, when comparing to original +3
port #FF (255)
  OUT IN
bit 0 not used not used
bit 1 not used not used
bit 2 not used not used
bit 3 not used not used
bit 4 not used not used
bit 5 not used not used
bit 6 not used not used
bit 7 not used n/ACTIVE_WINDOW (H border AND-ed with V border)

All the other +3 ports (#0FFD for parallel printer, #2FFD & #3FFD for FDD interface and #BFFD & FFFD for PSG interface) are implemented exactly the same as on original +3.

Custom I/O ports, not found on original Spectrum hardware

All of these new ports have read capabilities (i.e. an IN #xxxx instruction will read the actual status of that #xxxx port).

port #7F7E (32638)
  OUT IN
  bit value = 0
(default at any RESET)
bit value = 1  
bit 0 ROM page 0 at address 0000-3FFF * RAM page 12 at address 0000-3FFF * actual bit status
bit 1 ROM page 1 at address 0000-3FFF * RAM page 13 at address 0000-3FFF * actual bit status
bit 2 ROM page 2 at address 0000-3FFF * RAM page 14 at address 0000-3FFF * actual bit status
bit 3 ROM page 3 at address 0000-3FFF * RAM page 15 at address 0000-3FFF * actual bit status
bit 4 write enable RAM pages 12-15
when in ROM mode
write disable RAM pages 12-15
when in ROM mode
actual bit status
bit 5 48K lock enable 48K lock disable actual bit status
bit 6 normal H border normal H suppressed actual bit status
bit 7 normal V border normal V suppressed actual bit status
* Actual ROM (or RAM in ROM mode) page at address 0000-3FFF depends on original +3 ports #1FFD and #7FFD status
port #BF7E (49022)
  OUT IN
  bit value = 0
(default at any RESET)
bit value = 1  
bit 0 write enable video RAM
for first 8K of page 5
write disable video RAM
for first 8K of page 5
actual bit status
bit 1 write enable video RAM
for first 8K of page 7
write disable video RAM
for first 8K of page 7
actual bit status
bit 2 write enable video RAM
for second 8K of page 5 & 7
write disable video RAM
for second 8K of page 5 & 7
actual bit status
bit 3 write enable video RAM
for pages 4 & 6
write disable video RAM
for pages 4 & 6
actual bit status
bit 4 write enable main RAM
for pages 4-7
write disable main RAM
for pages 4-7
actual bit status
bit 5 CPU reads pages 4-7
from main RAM
CPU reads pages 4-7
from video RAM
actual bit status
bit 6 normal H resolution double H resolution actual bit status
bit 7 video RAM is written by CPU video RAM is written by external
serial data
actual bit status
port #DF7E (57214)
  OUT IN
  bit value = 0
(default at any RESET)
bit value = 1  
bit 0 currently not used currently not used actual bit status
bit 1 currently not used currently not used actual bit status
bit 2 currently not used currently not used actual bit status
bit 3 extends main RAM to 256K at address C000-FFFF (+3 mode)
or 4000-7FFF (CP/M Plus mode)
actual bit status
bit 4 extends main RAM to 512K at address C000-FFFF (+3 mode)
or 4000-7FFF (CP/M Plus mode)
actual bit status
bit 5 extends main RAM to 1024K at address C000-FFFF (+3 mode)
or 4000-7FFF (CP/M Plus mode)
actual bit status
bit 6 extends main RAM to 2048K at address C000-FFFF (+3 mode)
or 4000-7FFF (CP/M Plus mode)
actual bit status
bit 7 extends main RAM to 4096K at address C000-FFFF (+3 mode)
or 4000-7FFF (CP/M Plus mode)
actual bit status
port #EF7E (61310)
  OUT IN
  bit value = 0
(default at any RESET)
bit value = 1  
bit 0 00 - no change, allows hardware switching
01 - force 3.5 MHz CPU clock
10 - force 7 MHz CPU clock
11 - force 14 MHz CPU clock
actual bit status
bit 1 actual bit status
bit 2 00 - no change, allows hardware switching
01 - force local free run oscillator for video circuits
10 - force external oscillator for video circuits
11 - does nothing (considered as invalid)
actual bit status
bit 3 actual bit status
bit 4 00 - display is 50 Hz / 313 lines
01 - display is 50 Hz / 312 lines
10 - display is 25 Hz / 625 lines interlaced (TV standard)
11 - display is 25 Hz / 625 lines interlaced (TV standard)
actual bit status
bit 5 actual bit status
bit 6 tape IN port is free tape IN port is AND-ed with tape OUT actual bit status
bit 7 Kempston joystick disable Kempston joystick enable actual bit status

Screen coverage of Video RAM addresses

Under construction


(iii) Drawings

I was once asked about the drawings, if they are “open” or somehow otherwise available.

The drawings are “open” since long time, except that I never managed to (re)draw and organize them in a PCB-oriented application (some of them are actually drawn in Visio) and too lazy to scan the remaining hand drawn. I also find hard to believe that someone will ever care about such a hard-wired complexity in year 201x (although not impossible), given the evolution of logic gate arrays. All what I can say is that I am still have much more fun in building pure hardware logic circuit connections than making logic emulation via software array programming.

But anyway, the drawings (at least the major part of it) are as follows:

I am particularly content with my solution for processor speed clock synchronous switching (drawing 03) and the double-buffer solution for data & address buses that allows the processor to write to video RAM without using any WAIT states up to approx 9.2MHz processor clock (drawing 07 & 08).

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